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low noise, high speed amplifier for 16-bit systems ad8021 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features low noise 2.1 nv/hz input voltage noise 2.1 pa/hz input current noise custom compensation constant bandwidth from g = ?1 to g = ?10 high speed 200 mhz (g = ?1) 190 mhz (g = ?10) low power 34 mw or 6.7 ma typical for 5 v supply output disable feature, 1.3 ma low distortion ?93 dbc second harmonic, f c = 1 mhz ?108 dbc third harmonic, f c = 1 mhz dc precision 1 mv maximum input offset voltage 0.5 v/c input offset voltage drift wide supply range, 5 v to 24 v low price small packaging available in soic-8 and msop-8 applications adc preamps and drivers instrumentation preamps active filters portable instrumentation line receivers precision instruments ultrasound signal processing high gain circuits general description the ad8021 is an exceptionally high performance, high speed voltage feedback amplifier that can be used in 16-bit resolution systems. it is designed to have both low voltage and low current noise (2.1 nv/hz typical and 2.1 pa/hz typical) while operating at the lowest quiescent supply current (7 ma @ 5 v) among todays high speed, low noise op amps. the ad8021 operates over a wide range of supply voltages from 2.25 v to 12 v, as well as from single 5 v supplies, making it ideal for high speed, low power instruments. an output disable pin allows further reduction of the quiescent supply current to 1.3 ma. connection diagram 8 7 6 5 1 2 3 4 logic reference ?in +in ?v s disable +v s v out c comp ad8021 01888-001 figure 1. soic-8 (r-8) and msop-8 (rm-8) the ad8021 allows the user to choose the gain bandwidth product that best suits the application. with a single capacitor, the user can compensate the ad8021 for the desired gain with little trade-off in bandwidth. the ad8021 is a well-behaved amplifier that settles to 0.01% in 23 ns for a 1 v step. it has a fast overload recovery of 50 ns. the ad8021 is stable over temperature with low input offset voltage drift and input bias current drift, 0.5 v/c and 10 na/c, respectively. the ad8021 is also capable of driving a 75 line with 3 v video signals. the ad8021 is both technically superior and priced considerably less than comparable amps drawing much higher quiescent current. the ad8021 is a high speed, general-purpose amplifier, ideal for a wide variety of gain configurations and can be used throughout a signal processing chain and in control loops. the ad8021 is available in both standard 8-lead soic and msop packages in the industrial temperature range of ?40c to +85c. frequency (hz) 0.1m 1g 1m 10m 100m closed-loop gain (db) 24 21 ?6 18 15 12 9 6 3 0 ?3 v out = 50mv p-p g = ?10, r f = 1k , r g = 100 , r in = 100 , c c = 0pf g = ?5, r f = 1k , r g = 200 , r in = 66.5 , c c = 1.5pf g = ?2, r f = 499 , r g = 249 , r in = 63.4 , c c = 4pf g = ?1, r f = 499 , r g = 499 , r in = 56.2 , c c = 7pf 01888-002 figure 2. small signal frequency response
ad8021 rev. f | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 connection diagram ....................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 7 maximum power dissipation ..................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 test circ u its ................................................................................. 17 applications ..................................................................................... 19 using the disable feature .......................................................... 20 theory of operation ...................................................................... 21 pcb layout considerations ...................................................... 21 driving 16-bit adcs ................................................................. 22 differential driver ...................................................................... 22 using the ad8021 in active filters ......................................... 23 driving capacitive loads .......................................................... 23 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 5/06rev. e to rev. f updated format..................................................................universal changes to general description .................................................... 1 changes to figure 3.......................................................................... 7 changes to figure 60...................................................................... 19 changes to table 9.......................................................................... 23 3/05rev. d to rev. e updated format..................................................................universal change to figure 19 ....................................................................... 11 change to figure 25 ....................................................................... 12 change to table 7 and table 8 ...................................................... 22 change to driving 16-bit adcs section .................................... 22 10/03rev. c to rev. d updated format..................................................................universal 7/03rev. b to rev. c deleted all references to evaluation board...................universal replaced figure 2 ..............................................................................5 updated outline dimensions....................................................... 20 2/03rev. a to rev. b edits to evaluation board applications....................................... 20 edits to figure 17 ........................................................................... 20 6/02rev. 0 to rev. a edits to specifications .......................................................................2
ad8021 rev. f | page 3 of 28 specifications v s = 5 v, @ t a = 25c, r l = 1 k, gain = +2, unless otherwise noted. table 1. ad8021ar/ad8021arm parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth g = +1, c c = 10 pf, v o = 0.05 v p-p 355 490 mhz g = +2, c c = 7 pf, v o = 0.05 v p-p 160 205 mhz g = +5, c c = 2 pf, v o = 0.05 v p-p 150 185 mhz g = +10, c c = 0 pf, v o = 0.05 v p-p 110 150 mhz slew rate, 1 v step g = +1, c c = 10 pf 95 120 v/s g = +2, c c = 7 pf 120 150 v/s g = +5, c c = 2 pf 250 300 v/s g = +10, c c = 0 pf 380 420 v/s settling time to 0.01% v o = 1 v step, r l = 500 23 ns overload recovery (50%) 2.5 v input step, g = +2 50 ns distortion/noise performance f = 1 mhz hd2 v o = 2 v p-p ?93 dbc hd3 v o = 2 v p-p ?108 dbc f = 5 mhz hd2 v o = 2 v p-p ?70 dbc hd3 v o = 2 v p-p ?80 dbc input voltage noise f = 50 khz 2.1 2.6 nv/hz input current noise f = 50 khz 2.1 pa/hz differential gain error ntsc, r l = 150 0.03 % differential phase error ntsc, r l = 150 0.04 degrees dc performance input offset voltage 0.4 1.0 mv input offset voltage drift t min to t max 0.5 v/c input bias current +input or ?input 7.5 10.5 a input bias current drift 10 na/c input offset current 0.1 0.5 a open-loop gain 82 86 db input characteristics input resistance 10 m common-mode input capacitance 1 pf input common-mode voltage range ?4.1 to +4.6 v common-mode rejection ratio v cm = 4 v ?86 ?98 db output characteristics output voltage swing ?3.5 to +3.2 ?3.8 to +3.4 v linear output current 60 ma short-circuit current 75 ma capacitive load drive for 30% overshoot v o = 50 mv p-p/1 v p-p 15/120 pf disable characteristics off isolation f = 10 mhz ?40 db turn-on time v o = 0 v to 2 v, 50% logic to 50% output 45 ns turn-off time v o = 0 v to 2 v, 50% logic to 50% output 50 ns disable voltageoff/on v disable ? v logic reference 1.75/1.90 v enabled leakage current logic reference = 0.4 v 70 a disable = 4.0 v 2 a
ad8021 rev. f | page 4 of 28 ad8021ar/ad8021arm parameter conditions min typ max unit disabled leakage current logic reference = 0.4 v 30 a disable = 0.4 v 33 a power supply operating range 2.25 5 12.0 v quiescent current output enabled 7.0 7.7 ma output disabled 1.3 1.6 ma +power supply rejection ratio v cc = 4 v to 6 v, v ee = ?5 v ?86 ?95 db ?power supply rejection ratio v cc = 5 v, v ee = ?6 v to ?4 v ?86 ?95 db v s = 12 v, @ t a = 25c, r l = 1 k, gain = +2, unless otherwise noted. table 2. ad8021ar/ad8021arm parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth g = +1, c c = 10 pf, v o = 0.05 v p-p 520 560 mhz g = +2, c c = 7 pf, v o = 0.05 v p-p 175 220 mhz g = +5, c c = 2 pf, v o = 0.05 v p-p 170 200 mhz g = +10, c c = 0 pf, v o = 0.05 v p-p 125 165 mhz slew rate, 1 v step g = +1, c c = 10 pf 105 130 v/s g = +2, c c = 7 pf 140 170 v/s g = +5, c c = 2 pf 265 340 v/s g = +10, c c = 0 pf 400 460 v/s settling time to 0.01% v o = 1 v step, r l = 500 21 ns overload recovery (50%) 6 v input step, g = +2 90 ns distortion/noise performance f = 1 mhz hd2 v o = 2 v p-p ?95 dbc hd3 v o = 2 v p-p ?116 dbc f = 5 mhz hd2 v o = 2 v p-p ?71 dbc hd3 v o = 2 v p-p ?83 dbc input voltage noise f = 50 khz 2.1 2.6 nv/hz input current noise f = 50 khz 2.1 pa/hz differential gain error ntsc, r l = 150 0.03 % differential phase error ntsc, r l = 150 0.04 degrees dc performance input offset voltage 0.4 1.0 mv input offset voltage drift t min to t max 0.2 v/c input bias current +input or ?input 8 11.3 a input bias current drift 10 na/c input offset current 0.1 0.5 a open-loop gain 84 88 db input characteristics input resistance 10 m common-mode input capacitance 1 pf input common-mode voltage range ?11.1 to +11.6 v common-mode rejection ratio v cm = 10 v ?86 ?96 db
ad8021 rev. f | page 5 of 28 ad8021ar/ad8021arm parameter conditions min typ max unit output characteristics output voltage swing ?10.2 to +9.8 ?10.6 to +10.2 v linear output current 70 ma short-circuit current 115 ma capacitive load drive for 30% overshoot v o = 50 mv p-p/1 v p-p 15/120 pf disable characteristics off isolation f = 10 mhz ?40 db turn-on time v o = 0 v to 2 v, 50% logic to 50% output 45 ns turn-off time v o = 0 v to 2 v, 50% logic to 50% output 50 ns disable voltageoff/on v disable ? v logic reference 1.80/1.95 v enabled leakage current logic reference = 0.4 v 70 a disable = 4.0 v 2 a disabled leakage current logic reference = 0.4 v 30 a disable = 0.4 v 33 a power supply operating range 2.25 5 12.0 v quiescent current output enabled 7.8 8.6 ma output disabled 1.7 2.0 ma +power supply rejection ratio v cc = 11 v to 13 v, v ee = ?12 v ?86 ?96 db ?power supply rejection ratio v cc = 12 v, v ee = ?13 v to ?11 v ?86 ?100 db v s = 5 v, @ t a = 25c, r l = 1 k, gain = +2, unless otherwise noted. table 3. ad8021ar/ad8021arm parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth g = +1, c c = 10 pf, v o = 0.05 v p-p 270 305 mhz g = +2, c c = 7 pf, v o = 0.05 v p-p 155 190 mhz g = +5, c c = 2 pf, v o = 0.05 v p-p 135 165 mhz g = +10, c c = 0 pf, v o = 0.05 v p-p 95 130 mhz slew rate, 1 v step g = +1, c c = 10 pf 80 110 v/s g = +2, c c = 7 pf 110 140 v/s g = +5, c c = 2 pf 210 280 v/s g = +10, c c = 0 pf 290 390 v/s settling time to 0.01% v o = 1 v step, r l = 500 28 ns overload recovery (50%) 0 v to 2.5 v input step, g = +2 40 ns distortion/noise performance f = 1 mhz hd2 v o = 2 v p-p ?84 dbc hd3 v o = 2 v p-p ?91 dbc f = 5 mhz hd2 v o = 2 v p-p ?68 dbc hd3 v o = 2 v p-p ?81 dbc input voltage noise f = 50 khz 2.1 2.6 nv/hz input current noise f = 50 khz 2.1 pa/hz
ad8021 rev. f | page 6 of 28 ad8021ar/ad8021arm parameter conditions min typ max unit dc performance input offset voltage 0.4 1.0 mv input offset voltage drift t min to t max 0.8 v/c input bias current +input or ?input 7.5 10.3 a input bias current drift 10 na/c input offset current 0.1 0.5 a open-loop gain 72 76 db input characteristics input resistance 10 m common-mode input capacitance 1 pf input common-mode voltage range 0.9 to 4.6 v common-mode rejection ratio 1.5 v to 3.5 v ?84 ?98 db output characteristics output voltage swing 1.25 to 3.38 1.10 to 3.60 v linear output current 30 ma short-circuit current 50 ma capacitive load drive for 30% overshoot v o = 50 mv p-p/1 v p-p 10/120 pf disable characteristics off isolation f = 10 mhz ?40 db turn-on time v o = 0 v to 1 v, 50% logic to 50% output 45 ns turn-off time v o = 0 v to 1 v, 50% logic to 50% output 50 ns disable voltageoff/on v disable ? v logic reference 1.55/1.70 v enabled leakage current logic reference = 0.4 v 70 a disable = 4.0 v 2 a disabled leakage current logic reference = 0.4 v 30 a disable = 0.4 v 33 a power supply operating range 2.25 5 12.0 v quiescent current output enabled 6.7 7.5 ma output disabled 1.2 1.5 ma +power supply rejection ratio v cc = 4.5 v to 5.5 v, v ee = 0 v ?74 ?82 db ?power supply rejection ratio v cc = 5 v, v ee = ?0.5 v to +0.5 v ?76 ?84 db
ad8021 rev. f | page 7 of 28 absolute maximum ratings table 4. parameter rating supply voltage 26.4 v power dissipation observed power derating curves input voltage (common mode) v s 1 v differential input voltage 1 0.8 v differential input current 10 ma output short-circuit duration observed power derating curves storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c 1 the ad8021 inputs are protected by diodes. current-limiting resistors are not used to preserve the low noise. if a differential input exceeds 0.8 v, the input current should be limited to 10 ma. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum power that can be safely dissipated by the ad8021 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. while the ad8021 is internally short-circuit protected, this can not be sufficient to guarantee that the maximum junction tem- perature (150c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. ambient temperature (c) maximum power dissipation (w) 2.0 1.5 1.0 0.5 0.01 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 8 5 8-lead soic 8-lead msop 01888-004 figure 3. maximum power dissipation vs. temperature 1 1 specification is for device in free air: 8-lead soic: ja = 125c/w; 8-lead msop: ja = 145c/w. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8021 rev. f | page 8 of 28 pin configuration and fu nction descriptions 8 7 6 5 1 2 3 4 logic reference ?in +in ?v s disable +v s v out c comp ad8021 01888-003 figure 4. pin configuration table 5. pin function descriptions pin o. nemonic description 1 logic reference reference for pin 8 1 voltage level. connect to logic low supply. 2 ?in inverting input. 3 +in noninverting input. 4 ?v s negative supply voltage. 5 c comp compensation capacitor. tie to ?v s . (see the applications section for value.) 6 v out output. 7 +v s positive supply voltage. 8 disable disable, active low . 1 when pin 8 ( disable ) is higher than pin 1 (logic reference) by approximately 2 v or more, the part is enab led. when pin 8 is brought down to withi n about 1.5 v of pin 1, the part is disabled. (see the specifications tables for exact disable and enable voltage levels.) if the disable featur e is not going to be used, pin 8 can be tied to +v s or a logic high source, and pin 1 can be tied to ground or logic low. alternatively, if pin 1 and pin 8 are not connected, the part is in an enabled state.
ad8021 rev. f | page 9 of 28 typical performance characteristics t a = 25c, v s = 5 v, r l = 1 k, g = +2, r f = r g = 499 , r s = 49.9 , r o = 976 , r d = 53.6 , c c = 7 pf, c l = 0, c f = 0, v out = 2 v p-p, frequency = 1 mhz, unless otherwise noted. frequency (hz) 0.1m 1g 1m 10m 100m closed-loop gain (db) 24 21 ?6 18 15 12 9 6 3 0 ?3 g = +10, r f = 1k ? , r g = 110 ? , c c = 0pf g = +5, r f = 1k ? , r g = 249 ? , c c = 2pf g = +2, r f = r g = 499 ? , c c = 7pf g = +1, r f = 75 ? , c c = 10pf 01888-005 figure 5. small signal frequency response vs. frequency and gain, v out = 50 mv p-p, noninverting (see figure 48 ) frequency (hz) 0.1m 1g 1m 10m 100m gain (db) 24 21 ?6 18 15 12 9 6 3 0 ?3 g = ?10, r f = 1k : , r g = 100 : , r in = 100 : , c c = 0pf g = ?5, r f = 1k : , r g = 200 : , r in = 66.5 : , c c = 1.5pf g = ?2, r f = 499 : , r g = 249 : , r in = 63.4 : , c c = 4pf g = ?1, r f = 499 : , r g = 499 : , r in = 56.2 : , c c = 7pf 01888-006 figure 6. small signal frequency response vs. frequency and gain, v out = 50 mv p-p inverting (see figure 48 ) frequency (hz) 0.1m 1g 1m gain (db) 10m 100m 9 8 ?1 7 6 5 4 3 2 1 0 c c = 9pf g = +2 c c = 7pf c c = 7pf c c = 9pf c c = 5pf 01888-007 figure 7. small signal frequency response vs. frequency and compensation capacitor, v out = 50 mv p-p (see figure 48 ) frequency (hz) 1g 1m gain (db) 10m 100m 9 8 ?1 7 6 5 4 3 2 1 0 g = +2 v s = 5v v s = 12v v s = 2.5v v s = 2.5v 01888-008 figure 8. small signal frequency response vs. frequency and supply, v out = 50 mv p-p, noninverting (see figure 48 ) frequency (hz) 1g 1m gain (db) 10m 100m 3 2 ?7 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v s = 5v v s = 2.5v v s = 2.5v g = ?1 v s = 12v 01888-009 figure 9. small signal frequency response vs. frequency and supply, v out = 50 mv p-p, inverting (see figure 50 ) frequency (hz) 1g 1m gain (db) 10m 100m 9 8 ?1 7 6 5 4 3 2 1 0 v out = 1v p-p v out = 4v p-p v out = 0.1v and 50mv p-p g = +2 01888-010 figure 10. frequency response vs. frequency and v out , noninverting (see figure 48 )
ad8021 rev. f | page 10 of 28 frequency (hz) 0.1m 1g 1m gain (db) 10m 100m 9 8 7 6 5 4 3 2 1 0 10 r l = 1k ? g = +2 r l = 100 ? 01888-011 figure 11. large signal frequency response vs. frequency and load, noninverting (see figure 49 ) frequency (hz) 1g 1m gain (db) 10m 100m 9 8 7 6 5 4 3 2 1 0 ?1 g = +2 +85c ?40c +25c +85c v out = 2v p-p v out = 50mv p-p ?40c +25c 01888-012 figure 12. frequency response vs. frequency, temperature, and v out , noninverting (see figure 48 ) frequency (hz) 1g 1m gain (db) 10m 100m 15 12 9 6 3 0 ?3 ?6 ?9 ?12 18 g = +2 50pf 30pf 20pf 10pf 0pf 01888-013 figure 13. small signal frequency response vs. frequency and capacitive load, noninverting, v out = 50 mv p-p (see figure 49 and figure 71 ) frequency (hz) 1g 0.1m 10m 100m gain (db) 9 8 7 6 5 4 3 2 1 0 10 1m r f = 1k ? and c f = 2.2pf g = +2 r f = r g r f = 150 ? r f = 1k ? r f = 499 ? r f = 250 ? r f = 75 ? 01888-014 figure 14. small signal frequency response vs. frequency and r f , noninverting, v out = 50 mv p-p (see figure 48 ) frequency (hz) 0.1m 1g 1m gain (db) 10m 100m 12 9 6 3 0 ?3 ?6 ?9 ?12 ?15 15 g = +2 r s = 49.9 ? r s = 100 ? r s = 249 ? 01888-015 figure 15. small signal frequency response vs. frequency and r s , noninverting, v out = 50 mv p-p (see figure 48 ) frequency (hz) 100k 1g 1m open-loop gain (db) 10m 100m 100 90 80 70 60 50 40 30 20 10 0 phase (degrees) 90 45 0 ?45 ?90 ?135 135 180 10k 01888-016 figure 16. open-loop gain and phase vs. frequency, r g = 100 , r f = 1 k, r o = 976 , r d = 53.6 , c c = 0 pf (see figure 50 )
ad8021 rev. f | page 11 of 28 frequency (hz) 1m gain (db) 10m 100m 6.2 6.0 5.8 5.6 5.4 6.4 g = +2 v s = 12v v s = 2.5v 01888-017 v s = 5v figure 17. 0.1 db flatness vs. frequency and supply, v out = 1 v p-p, r l = 150 , noninverting (see figure 49 ) frequency (hz) 0.1m distortion (dbc) 1m ?40 ?60 ?90 ?110 ?130 ?20 ?30 ?50 ?70 ?80 ?100 ?120 10m 20m third second r l = 100 r l = 1k 01888-018 figure 18. second and third harmonic distortion vs. frequency and r l frequency (hz) 100k distortion (dbc) 1m 20m ?40 ?60 ?90 ?110 ?130 ?30 ?50 ?70 ?80 ?100 ?120 10m third second second second third v s = 2.5v v s = 5v v s = 12v 01888-019 figure 19. second and third harmonic distortion vs. frequency and v s frequency (mhz) 9.5 p out (dbm) 10.5 ?40 ?60 ?90 ?110 ?30 ?50 ?70 ?80 ?100 ?120 ?20 9.7 10.3 10.0 f = 0.2mhz f 1 f 2 976 53.6 50 p out 01888-020 figure 20. intermodulation distortion vs. frequency frequency (mhz) 0 third-order intercept (dbm) 10 20 45 30 25 40 35 20 50 v s = 5v v s = 2.5v 51 5 01888-021 figure 21. third-order intercept vs. frequency and supply voltage 1 distortion (dbc) ?60 ?90 ?100 ?70 ?80 ?120 ?50 ?110 third second second third v out (v p-p) 2345 6 r l = 100 r l = 1k 01888-022 figure 22. second and third harmonic distortion vs. v out and r l
ad8021 rev. f | page 12 of 28 f c = 5mhz f c = 1mhz 1 distortion (dbc) ?60 ?90 ?100 ?70 ?80 ?120 ?50 ?110 third second second third v out (v p-p) 2345 01888-023 6 figure 23. second and third harmonic distortion vs. v out and fundamental frequency (f c ), g = +2 1 distortion (dbc) ?50 ?80 ?90 ?60 ?70 ?110 ?40 ?100 third second second third v out (v p-p) 2345 6 f c = 5mhz f c = 1mhz 01888-024 figure 24. second and third harmonic distortion vs. v out and fundamental frequency (f c ), g = +10 0 400 800 ?90 ?110 ?80 200 600 1000 ?120 ?70 ?100 distortion (dbc) feedback resistance ( ) f c = 1mhz r l = 1k r f = r g g = +2 third second 01888-025 figure 25. second and third harmonic distortion vs. feedback resistor (r f ) 0 800 1600 3.2 2.9 3.4 400 1200 2000 2.8 3.5 3.1 3.3 3.0 ?3.4 ?3.7 ?3.2 ?3.8 ?3.1 ?3.5 ?3.3 ?3.6 negative output positive output load ( ) positive output voltage (v) negative output voltage (v) 01888-026 figure 26. dc output voltages vs. load (see figure 48 ) ?50 ?10 30 ?30 10 50 70 90 110 60 0 100 120 40 80 20 v s = 12v v s = 5.0v v s = 2.5v temperature (c) short-circuit current (ma) 01888-027 figure 27. short-circuit current to ground vs. temperature g = 2 r l = 1k , 150 50 40 30 20 10 ?10 ?20 ?30 ?40 ?50 120 160 200 time (ns) 80 40 0 v out (mv) 01888-028 figure 28. small signal transient response vs. r l , v o = 50 mv p-p, noninverting (see figure 49 )
ad8021 rev. f | page 13 of 28 r l = 150 2.0 1.0 ?1.0 ?2.0 120 160 200 time (ns) 01888-029 r l = 1k v o = 4v p-p g = 2 v out (v) 80 40 0 figure 29. large signal transient response vs. r l , noninverting (see figure 49 ) v out v in 5 4 3 2 1 ?1 ?2 ?3 ?4 ?5 volts 100 150 200 250 time (ns) v o = 4v p-p g = ?1 01888-030 50 0 figure 30. large signal transient response, inverting (see figure 50 ) 2.0 1.0 ?1.0 ?2.0 120 160 200 time (ns) c l = 50pf g = 2 c l = 10pf, 0pf v o = 4v p-p 80 40 0 01888-031 v out (v) figure 31. large signal transient response vs. c l (see figure 48 ) v out (v) 2.0 1.0 ?1.0 ?2.0 120 160 200 time (ns) v o = 2v p-p g = 2 v s = 2.5v v s = 5v 80 40 0 01888-032 figure 32. large signal transient response vs. v s (see figure 48 ) v in 0 100 200 300 400 500 time (ns) 01888-033 v in = 3v g = +2 v in = 1v/div v out = 2v/div v out , r l = 1k r l = 150 figure 33. overdrive recovery vs. r l (see figure 49 ) 25ns ?0.01% +0.01% hor = 5ns/div g = 2 output settling 01888-034 vert = 0.2mv/div figure 34. 0.01% settling time, 2 v step
ad8021 rev. f | page 14 of 28 time (s) 12 settling (v) 20 28 ?100 24 ?80 ?60 ?40 ?20 0 20 40 60 80 100 04 8 16 32 01888-035 pulse width = 300s pulse width = 120ns t 1 5v 0v figure 35. long-term settling, 0 v to 5 v, v s = 12 v, g = +13 g = +1 50 40 30 20 10 ?10 ?20 ?30 ?40 ?50 120 160 200 time (ns) 01888-036 80 40 0 v out (mv) figure 36. small signal transient response, v o = 50 mv p-p, g = +1 (see figure 48 ) 10m frequency (hz) 100 10 1 10 100 1k 10k 100k 1m 01888-037 voltage noise (nv/ hz) 2.1nv/ hz figure 37. input voltage noise vs. frequency frequency (hz) 100 10m 1k 10k 100k 100 1 10 10 1m 01888-038 input current noise (pa/ hz) figure 38. input current noise vs. frequency ?25 100 25 voltage offset (mv) 50 75 0.48 0.24 ?50 0 0.44 0.40 0.36 0.32 0.28 01888-039 temperature (c) figure 39. v os vs. temperature ?25 100 25 input bias current ( a) 50 75 8.4 6.0 ?50 0 8.0 7.6 7.2 6.8 6.4 01888-040 temperature (c) figure 40. input bias current vs. temperature
ad8021 rev. f | page 15 of 28 100k 10m 100m ?20 10k 1m ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 01888-041 frequency (hz) cmrr (db) figure 41. cmrr vs. frequency (see figure 51 ) 100k 1g 10m 100m 300 10k 1m 100 30 10 3 1 0.3 0.1 0.03 0.01 0.003 01888-042 frequency (hz) output impedance ( ) figure 42. output impedance vs. frequency, chip enabled (see figure 52 ) 4v 2v 2v 1v 0 100 200 300 400 500 time (ns) 01888-043 v output t en = 45ns t dis = 50ns disable figure 43. enable (t en )/disable (t dis ) time vs. v out (see figure 53 ) 1m 1g 100m 0 0.1m 10m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 01888-044 disabled isolation (db) frequency (hz) figure 44. input-to-output isolation, chip disabled (see figure 54 ) 01888-045 100k 1g 10m 100m 300k 10k 1m 100k 30k 10k 3k 1k 300 100 30 10 3 frequency (hz) output impedance ( ) figure 45. output impedance vs. frequency, chip disabled (see figure 55 ) 1m 500m 100m 10k 10m 100k psrr (db) 0 ?10 ?30 ?50 ?70 ?80 ?100 ?20 ?40 ?60 ?90 01888-046 v s = 2.5v v s = 12v v s = 5v frequency (hz) ?psrr +psrr figure 46. psrr vs. frequency and supply voltage (see figure 56 and figure 57 )
ad8021 rev. f | page 16 of 28 0 100 50 8.5 ?50 25 8.0 7.5 7.0 6.5 6.0 5.5 75 ?25 01888-047 temperature (c) supply current (ma) figure 47. quiescent supply current vs. temperature
ad8021 rev. f | page 17 of 28 test circuits 50 ?v s c c +v s 5 r s r o r d r f c f r g r in 49.9 50 cable 50 cable 01888-048 figure 48. noninverting gain fet probe 5 50 ?v s c c +v s r s r l r f c f r g r in 49.9 50 cable c l 01888-049 figure 49. noninverting gain and fet probe 5 50 ?v s c c +v s r o r f r d r g r in 49.9 50 cable 49.9 50 cable 01888-050 figure 50. inverting gain 01888-051 hp8753d 50 ad8021 499 499 55.6 499 499 49.9 network analyzer c c 5 +v s 7pf 50 ?v s figure 51. cmrr 5 hp8753d ad8021 100 network analyzer c c +v s 50 ?v s 7pf r g 499 r f 499 01888-052 figure 52. output impedance, chip enabled 01888-053 499 ad8021 49.9 49.9 7pf c c 5 976 1 8 1.0v 49.9 499 4v 53.6 +v s ?v s logic ref disable figure 53. enable/disable 01888-054 7pf 5 1 8 hp8753d 50 ad8021 499 499 1k 49.9 network analyzer c c +v s 50 ?v s 49.9 50 cable fet probe logic ref disable figure 54. input-to-output isolation, chip disabled ad8021 1 8 5 7pf hp8753d 50 100 network analyzer c c +v s ?v s 01888-055 figure 55. output impedance, chip disabled
ad8021 rev. f | page 18 of 28 5 bias bnc hp8753d network analyzer 50 50 50 cable 49.9 , 5w +v s +v s c c 7pf 499 976 53.6 ?v s 249 499 01888-056 figure 56. positive psrr 49.9 5w 499 50 cable ?v s +v s c c 7pf 499 976 53.6 ?v s 249 bias bnc hp8753d network analyzer 50 50 5 01888-057 figure 57. negative psrr
ad8021 rev. f | page 19 of 28 applications the typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, c internal , using dominant pole compensation. to a first-order approximation, voltage feedback op amps have a fixed gain bandwidth product. for example, if its ?3 db bandwidth is 200 mhz for a gain of g = +1; at a gain of g = +10, its bandwidth is only about 20 mhz. the ad8021 is a voltage feedback op amp with a minimal c internal of about 1.5 pf. by adding an external compensation capacitor, c c , the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. unlike the typical op amp with fixed compensation, the ad8021 allows the user to: ? maximize the amplifier bandwidth for closed-loop gains between 1 and 10, avoiding the usual loss of bandwidth and slew rate. ? optimize the trade-off between bandwidth and phase margin for a particular application. ? match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in figure 65 ). frequency (hz) 1m open-loop gain (db) 100m 110 10k 10m 100 80 60 40 30 10 100k 90 70 50 20 1k 1g 10g 0 ?10 180 135 45 90 0 phase (degrees) (b) (c) (a) (a) (c) 86 c c = 0pf c c = 10pf 01888-058 (b) figure 58. simplified diagram of open-loop gain and phase response figure 58 is the ad8021 gain and phase plot that has been simplified for instructional purposes. arrow a in figure 58 shows a bandwidth of about 200 mhz and a phase margin at about 60 when the desired closed-loop gain is g = +1 and the value chosen for the external compensation capacitor is c c = 10 pf. if the gain is changed to g = +10 and c c is fixed at 10 pf, then (as expected for a typical op amp) the bandwidth is degraded to about 20 mhz and the phase margin increases to 90 (arrow b). however, by reducing c c to 0 pf, the bandwidth and phase margin return to about 200 mhz and 60 (arrow c), respectively. in addition, the slew rate is dramatically increased, as it roughly varies with the inverse of c c . 1 2 3 4 5 6 7 8 9 10 0 noise gain (v/v) 12 3 4 5 6 7 8 91011 01888-059 compensation capacitance (pf) figure 59. suggested compensati on capacitance vs. gain for maintaining 1 db peaking table 6 and figure 59 provide recommended values of com- pensation capacitance at various gains and the corresponding slew rate, bandwidth, and noise. note that the value of the compensation capacitor depends on the circuit noise gain, not the voltage gain. as shown in figure 60 , the noise gain, g n , of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or nonin- verting gain. thus, noninverting g n = r f / r g + 1 inverting g n = r f / r g + 1 + ? ? + noninverting ad8021 3 2 5 6 1 r s ?v s c comp g = g n = +5 r f 1k ? r g 249 ? ad8021 2 3 5 6 r f 1k? r g 249 ? ?v s c comp g = ?4 g n = +5 inverting 01888-060 figure 60. the noise gain of both is 5
ad8021 rev. f | page 20 of 28 c f = c l = 0, r l = 1 k, r in = 49.9 (see figure 49 ). table 6. recommended component values noise gain (noninverting gain) r s () r f () r g () c comp (pf) slew rate (v/s) ?3 db ss bw (mhz) output noise (ad8021 only) (nv/hz) output noise (ad8021 with resistors) (nv/hz) 1 75 75 na 10 120 490 2.1 2.8 2 49.9 499 499 7 150 205 4.3 8.2 5 49.9 1 k 249 2 300 185 10.7 15.5 10 49.9 1 k 110 0 420 150 21.2 27.9 20 49.9 1 k 52.3 0 200 42 42.2 52.7 100 49.9 1 k 10 0 34 6 211.1 264.1 with the ad8021, a variety of trade-offs can be made to fine- tune its dynamic performance. sometimes more bandwidth or slew rate is needed at a particular gain. reducing the compensation capacitance, as illustrated in figure 7 , increases the bandwidth and peaking due to a decrease in phase margin. on the other hand, if more stability is needed, increasing the compensation capacitor decreases the bandwidth while increasing the phase margin. as with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. often, the input capacitance (due to the op amp itself, as well as the pc board) has a significant effect. the feedback resistance, together with the input capacitance, can contribute to a loss of phase margin, thereby affecting the high frequency response, as shown in figure 14 . a capacitor (c f ) in parallel with the feedback resistor can compensate for this phase loss. additionally, any resistance in series with the source creates a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and capacitance), the effect of which is shown in figure 15 . it must also be noted that increasing resistor values increases the overall noise of the amplifier and that reducing the feedback resistor value increases the load on the output stage, thus increasing distortion (see figure 22 ). using the disable feature when pin 8 ( disable ) is higher than pin 1 (logic reference) by approximately 2 v or more, the part is enabled. when pin 8 is brought down to within about 1.5 v of pin 1, the part is disabled. see table 1 for exact disable and enable voltage levels. if the disable feature is not used, pin 8 can be tied to v s or a logic high source, and pin 1 can be tied to ground or logic low. alternatively, if pin 1 and pin 8 are not connected, the part is in an enabled state.
ad8021 rev. f | page 21 of 28 theory of operation the ad8021 is fabricated on the second generation of analog devices proprietary high voltage extra-fast complementary bipolar (xfcb) process, which enables the construction of pnp and npn transistors with similar f t s in the 3 ghz region. the transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. it also reduces nonlinear capaci- tance (a source of distortion) and allows a higher transistor, f t , for a given quiescent current. the supply current is trimmed, which results in less part-to-part variation of bandwidth, slew rate, distortion, and settling time. as shown in figure 61 , the ad8021 input stage consists of an npn differential pair in which each transistor operates at a 0.8 ma collector current. this allows the input devices a high transconductance; thus, the ad8021 has a low input noise of 2.1 nv/hz @ 50 khz. the input stage drives a folded cascode that consists of a pair of pnp transistors. the folded cascode and current mirror provide a differential-to-single-ended conversion of signal current. this current then drives the high impedance node (pin 5), where the c c external capacitor is connected. the output stage preserves this high impedance with a current gain of 5000, so that the ad8021 can maintain a high open-loop gain even when driving heavy loads. two internal diode clamps across the inputs (pin 2 and pin 3) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset voltage and input bias current. +in ?in c internal 1.5pf c comp c c ?v s +v s output 01888-061 figure 61. simpli fied schematic pcb layout considerations as with all high speed op amps, achieving optimum performance from the ad8021 requires careful attention to pc board layout. particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. otherwise, lead inductance can influence the frequency response and even cause high frequency oscillations. use of a multilayer printed circuit board, with an internal ground plane, reduces ground noise and enables a compact component arrangement. due to the relatively high impedance of pin 5 and low values of the compensation capacitor, a guard ring is recommended. the guard ring is simply a pc trace that encircles pin 5 and is connected to the output, pin 6, which is at the same potential as pin 5. this serves two functions. it shields pin 5 from any local circuit noise generated by surrounding circuitry. it also minimizes stray capacitance, which would tend to otherwise reduce the bandwidth. an example of a guard ring layout is shown in figure 62 . also shown in figure 62 , the compensation capacitor is located immediately adjacent to the edge of the ad8021 package, spanning pin 4 and pin 5. this capacitor must be a high quality surface- mount cog or npo ceramic. the use of leaded capacitors is not recommended. the high frequency bypass capacitor(s) should be located immediately adjacent to the supplies, pin 4 and pin 7. to achieve the shortest possible lead length at the inverting input, the feedback resistor r f is located beneath the board and spans the distance from the output, pin 6, to inverting input pin 2. the return node of resistor r g should be situated as close as possible to the return node of the negative supply bypass capacitor connected to pin 4. disable v out 8 7 6 1 2 3 logic reference ?in +in ?v s 4 +v s 5 c comp ground plane bypass capacitor compensation capacitor ground plane bypass c apacito r metal (top view) 01888-062 figure 62. recommended location of critical components and guard ring
ad8021 rev. f | page 22 of 28 driving 16-bit adcs low noise and adjustable compensation make the ad8021 especially suitable as a buffer/driver for high resolution adcs. as seen in figure 19 , the harmonic distortion is better than 90 dbc at frequencies between 100 khz and 1 mhz. this is an advantage for complex waveforms that contain high frequency information, because the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. the increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a sample. this advantage is particularly apparent when using 16-bit high resolution adcs with high sampling rates. figure 63 shows a typical adc driver configuration. the ad8021 is in an inverting gain of ?7.5, f c is 65 khz, and its output voltage is 10 v p-p. the results are listed in table 7 . + ? in hi in hi 50 r g 200 56pf r f 1.5k c c 10pf ?12v ad7665 570ksps 16 bits +5v 6 5 3 2 590 +12v ad8021 01888-063 figure 63. inverting adc driver, gain = ?7.5, f c = 65 khz table 7. summary of adc driver performance (f c = 65 khz, v out = 10 v p-p) parameter measurement unit second harmonic distortion ?101.3 dbc third harmonic distortion ?109.5 dbc thd ?100.0 dbc sfdr +100.3 dbc figure 64 shows another adc driver connection. the circuit was tested with a noninverting gain of 10.1 and an output voltage of approximately 20 v p-p for optimum resolution and noise performance. no filtering was used. an fft was performed using analog devices evaluation software for the ad7665 16-bit converter. the results are listed in table 8 . 50 +5v ad8021 + ? ?12v +12v ad7665 570ksps 50 3 2 r f 750 optional c f in lo in 6 50 hi adc c c 5 r g 82.5 16 bits 01888-064 figure 64. noninverting adc driver, gain = 10, f c = 100 khz table 8. summary of adc driver performance (f c = 100 khz, v out = 20 v p-p) parameter measurement unit second harmonic distortion ?92.6 dbc third harmonic distortion ?86.4 dbc thd ?84.4 dbc sfdr +5.4 dbc differential driver the ad8021 is uniquely suited as a low noise differential driver for many adcs, balanced lines, and other applications requiring differential drive. if pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter is higher than that of the follower section, resulting in an imbalance in the frequency response (see figure 66 ). a better solution takes advantage of the external compensation feature of the ad8021. by reducing the c comp value of the inverter, its bandwidth can be increased to match that of the follower, avoiding compromises in gain bandwidth and phase delay. the inverting and noninverting bandwidths can be closely matched using the compensation feature, thus minimizing distortion. figure 65 illustrates an inverter-follower driver circuit operating at a gain of 2, using individually compensated ad8021s. the values of feedback and load resistors were selected to provide a total load of less than 1 k, and the equivalent resistances seen at each op amps inputs were matched to minimize offset voltage and drift. figure 67 is a plot of the resulting ac responses of driver halves. ad8021 + ? 3 2 6 7pf 249 499 g = +2 499 49.9 1k v out1 5 ?v s ad8021 + ? 3 2 6 5pf 232 g = ?2 664 1k v out2 5 ?v s 332 v in 01888-065 figure 65. differential amplifier
ad8021 rev. f | page 23 of 28 g = ?2 g = +2 gain (db) frequency (hz) 100k 1m 10m 100m 1g 12 9 6 3 0 ?3 ?6 ?9 ?12 ?15 ?18 01888-066 figure 66. ac response of two identically compensated high speed op amps configured for a gain of +2 and a gain of ?2 100k 1m 10m 100m 1g frequency (hz) 12 9 6 3 0 ?3 ?6 ?9 ?12 ?15 ?18 gain (db) 01888-067 g = 2 figure 67. ac response of two dissimilarly compensated ad8021 op amps ( figure 66 ) configured for a gain of +2 and a gain of ?2, (note the close gain match) using the ad8021 in active filters the low noise and high gain bandwidth of the ad8021 make it an excellent choice in active filter circuits. most active filter literature provides resistor and capacitor values for various filters but neglects the effect of the op amps finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. unfortunately, real filters do not behave in this manner. instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency, pass-band performance. figure 68 shows the schematic of a 2-pole, low-pass active filter and lists typical component values for filters having a bessel- type response with a gain of 2 and a gain of 5. figure 69 is a network analyzer plot of this filters performance. c c c2 ad8021 3 2 r f 6 v out r g +v s r2r1 v in 5 ?v s c1 01888-068 figure 68. schematic of a second-order, low-pass active filter table 9. typical component values for second-order, low- pass active filter of figure 68 gain r1 () r2 () r f () r g () c1 (nf) c2 (nf) c c (pf) 2 71.5 215 499 499 10 10 7 5 44.2 365 365 90.9 10 10 2 1k 10k 100k 1m 10m frequency (hz) 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 gain (db) g = 2 g = 5 01888-069 figure 69. frequency response of the filter circuit of figure 68 for two different gains driving capacitive loads when the ad8021 drives a capacitive load, the high frequency response can show excessive peaking before it rolls off. two techniques can be used to improve stability at high frequency and reduce peaking. the first technique is to increase the compensation capacitor, c c , which reduces the peaking while maintaining gain flatness at low frequencies. the second technique is to add a resistor, r snub , in series between the output pin of the ad8021 and the capacitive load, c b l . shows the response of the ad8021 when both c figure 70 c and r snub b are used to reduce peaking. for a given c l , figure 71 can be used to determine the value of r snub that maintains 2 db of peaking in the frequency response. note, however, that using r b snub attenuates the low frequency output by a factor of r load /(r snub b + r load ).
ad8021 rev. f | page 24 of 28 obe 0.1 1000 10 100 frequency (mhz) gain (db) 18 16 14 12 10 8 6 4 2 0 499 499 1k 49.9 49.9 c c 33pf fet pr ?v s r snub +v s 5 6 1.0 01888-070 c c = 7pf; r snub = 0 c c = 8pf; r snub = 0 c c = 8pf; r snub = 17.4 r l figure 70. peaking vs. r snub and c c for c l = 33 pf 20 18 16 14 12 10 8 6 4 2 0 capacitive load (pf) 0 5 10 20 25 30 35 40 45 50 15 r snub ( ) 01888-071 figure 71. relationship of r snub vs. c b l for 2 db peaking at a gain of +2
ad8021 rev. f | page 25 of 28 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa figure 72. 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 73. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model temperature range package description package option branding ad8021ar ?40c to +85c 8-lead soic r-8 ad8021ar-reel ?40c to +85c 8-lead soic r-8 ad8021ar-reel7 ?40c to +85c 8-lead soic r-8 ad8021arz 1 ?40c to +85c 8-lead soic r-8 ad8021arz-reel 1 ?40c to +85c 8-lead soic r-8 ad8021arz-reel7 1 ?40c to +85c 8-lead soic r-8 ad8021arm ?40c to +85c 8-lead msop rm-8 hna ad8021arm-reel ?40c to +85c 8-lead msop rm-8 hna ad8021arm-reel7 ?40c to +85c 8-lead msop rm-8 hna ad8021armz 1 ?40c to +85c 8-lead msop rm-8 hna# AD8021ARMZ-REEL 1 ?40c to +85c 8-lead msop rm-8 hna# AD8021ARMZ-REEL7 1 ?40c to +85c 8-lead msop rm-8 hna# 1 z = pb-free part, # denotes lead-free product may be top or bottom marked.
ad8021 rev. f | page 26 of 28 notes
ad8021 rev. f | page 27 of 28 notes
ad8021 rev. f | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01888-0-5/06(f)

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